Circuit :  Nicholas Choong
Email :Nicholas Choong

Description
The idea is simply to turn off the negative voltage load. Some examples:-
- Bias votlages for LCD panels
- RF Amplifiers
- Audio Amplifiers

The good thing about this design is that i can make use of the system i/o voltage to control the on/off and this is the whole idea. However, there are many many type of load switches that turn of negative voltages. Here is the suggestion:

At the point A, the voltage is ramp from 2.2V to 2.6V and resulted to load to switch from ON to OFF

The theory of operation is pretty much a simple one. There are two NMOS and one PMOS. And the PMOS is at the interface to the i/o ON/OFF logic. One important observation is, the PMOS (U5) source terminal is bias at the 3V or the logic high voltage level. When the gate of the PMOS is 0V, the PMOS is turned on. At Point B, the voltage is 3V. This 3V will drive the NMOS gate (U2), as the U2 NMOS source is at the -5V (the negative voltage supply), the NMOS is being turned on and hence pull the gate of the NMOS U1 gate to ground. U1 swtich is turned on and the load voltage at Point D is -5V.

On the load turn off operation, the gate of PMOS is pulled to high. and PMOS will be off and resulted the rest of the NMOS are all in off status. Simple and easy. The advantage of this circuit are :-
- Of course, simple and easy
- can be low cost and not eating up spaces. as the U5 (PMOS) and U2 (NMOS) can accept very low cost MOSFETs. The example given are FDV301N and FDV302P or NDS332P that used in this example
- The selection of U1 is mainly depend oon load current requirements and if the load is very low, low cost NMOS can be used.

For further looking into this negative switch design, the transcient characteristic can be simulated when a pulse is asserted into gate of the PMOS.

the pulse in this simulation (diagram above, lower graph, green trace) is 0V to 3V with rise time and fall time of 2ms, and the pulse duration is 40ms. The load response is show in purple trace. During the turn off of the load, there is a high inrush current (diagram above, upper graph, green trace) that pulling away from the load from the ground. It is good to zoom into the inrush

This inrush happened during the PMOS is on the way turning off, but as the slope of the turn off is not directly causing the spike, it is something else. I have not done any simulation on the way to reduce or to improve the inrush as normally the application of the negative is mainly less than 100mA. And i am also very lazy...:). Should you need to use me to do more for you... drop me a mail